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exar corporation, 48720 kato road, fremont, ca 94538 ? (510) 668-7000 ? fax (510) 668-7017 st16c580 rev. 1.22 uart with 16-byte fifo?s and infrared (irda) encoder/decoder general description the st16c580 1 is a universal asynchronous receiver and transmitter (uart) and is pin compatible with the st16c550 uart. the 580 is an enhanced uart with 16 byte fifo?s, automatic hardware/software flow control, and data rates up to 1.5mbps. onboard status registers provide the user with error indications and operational status. modem interface control is included and can be optionally configured to operate with the infrared (irda) encoder/decoder. the system interrupts may be tailored to meet user requirements. an internal loop-back capability allows onboard diagnostics. the 580 is available in the 48 pin tqfp package. it is fabricated in an advanced cmos process to achieve low drain power and high speed requirements. features ? pin to pin and functionally compatible to the industry standard 16550 ? 2.97 to 5.5 volt operation ? 1.5 mbps transmit/receive operation (24mhz) ? 16 byte transmit fifo ? 16 byte receive fifo with error flags ? automatic hardware/software flow control ? programmable xon/xoff characters ? independent transmit and receive control ? software selectable baud rate generator pre- scaleable clock rates of 1x or 4x ? four selectable transmit/receive fifo interrupt trig- ger levels ? standard modem interface or infrared irda encode/ decoder interface ? sleep mode ( 200 a stand-by ) ? low operating current ( 1.2ma typ.) ordering information part number package operating temp device status st16c580cq48 48-lead tqfp 0 c to + 70 c active st16c580iq48 48-lead tqfp -40 c to + 85 c active *note 1 covered by u.s. patent #5,649,122. august 2005 48 pin tqfp package 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 n.c. d5 d6 d7 rclk n.c. rx tx cs0 cs1 -cs2 -baudout n.c. xtal1 xtal2 -iow iow gnd -ior ior n.c. -ddis -txrdy -as n.c. reset -op1 -dtr -rts -op2 int -rxrdy a0 a1 a2 n.c. n.c. d4 d3 d2 d1 d0 vcc -ri -cd -dsr -cts n.c. xr16c580cq48
st16c580 2 rev. 1.22 d0-d7 -ior,ior -iow,iow reset a0-a2 -as cs0,cs1 -cs2 int -rxrdy -txrdy -dtr,-rt s -op1,-op2 -cts -ri -cd -dsr tx rx data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers flow control logic transmit shift register receive fifo registers flow control logic receive shift register inter connect bus lines & control signals clock & baud rate generator xtal1 rclk xtal2 -baudout -ddis ir encoder ir decoder figure 2, block diagram
st16c580 3 rev. 1.22 symbol description a0 28 i address-0 select bit - internal registers address selection. a1 27 i address-1 select bit internal registers address selection. a2 26 i address-2 select bit internal registers address selection. ior 20 i read strobe. its function is the same as -ior (see -ior), except it is active high. either an active -ior or ior is required to transfer data from 580 to cpu during a read operation. cs0 9 i chip select-0. a logical 1 on this pin provides the chip select 0 function. cs1 10 i chip select-1. a logical 1 on this pin provides the chip select 1 function. -cs2 11 i chip select -2. a logical 0 on this pin provides the chip select 2 function. iow 17 i write strobe. a logic 1 transition creates a write strobe. its function is the same as -iow (see -iow), but it acts as an active high input signal. either -iow or iow is required to transfer data from the cpu to 580 during a write operation. -as 24 i address strobe. a logic 1 transition on -as latches the state of the chip selects and the register select bits, a0-a2. this input is used when address and chip selects are not stable for the duration of a read or write operation, i.e., a microprocessor that needs to de-multiplex the address and data bits. if not required, the -as input can be permanently tied to a logic 0 (it is edge triggered). d0-d7 43-47 2-4 i/o data bus (bi-directional) - these pins are the eight bit, three state data bus for transferring information to or from the controlling cpu. d0 is the least significant bit and the first data bit in a transmit or receive serial data stream. gnd 18 pwr signal and power ground. symbol pin signal pin description 48 type
st16c580 4 rev. 1.22 -ior 19 i read strobe (active low strobe). a logic 0 on this pin transfers the contents of the 580 data bus to the cpu. -iow 16 i write strobe (active low strobe) - a logic 0 on this pin transfers the contents of the cpu data bus to the addressed internal register. int 30 o interrupt request. -rxrdy 29 o receive ready. a logic 0 indicates receive data ready status, i.e. the rhr is full or the fifo has one or more rx characters available for unloading. this pin goes to a logic 0 when the fifo/rhr is full or when there are more characters available in either the fifo or rhr. -txrdy 23 o transmit ready. buffer ready status is indicated by a logic 0, i.e., at least one location is empty and available in the fifo or thr. this pin goes to a logic 1 when there are no more empty locations in the fifo or thr. -baudout 12 o baud rate generator output. this pin provides the 16x clock of the selected data rate from the baud rate generator. the rclk pin must be connected externally to -baudout when the receiver is operating at the same data rate. -ddis 22 o drive disable. this pin goes to a logic 0 when the external cpu is reading data from the 580. this signal can be used to disable external transceivers or other logic functions. -op1 34 o output-1 (user defined) - see bit-2 of modem control register (mcr bit-2). -op2 31 o output-2 (user defined). this pin provides the user a general purpose output. see bit-3 modem control register (mcr bit- 3). rclk 5 i receive clock input. this pin is used as external 16x clock input to the receiver section. external connection to - baudout pin is required in order to utilize the internal baud rate generator. symbol description symbol pin signal pin description 48 type
st16c580 5 rev. 1.22 reset 35 i reset. (active high) - a logic 1 on this pin will reset the internal registers and all the outputs. the uart transmitter output and the receiver input will be disabled during reset time. (see st16c580 external reset conditions for initialization de- tails.) vcc 42 pwr power supply input. xtal1 14 i crystal or external clock input - functions as a crystal input or as an external clock input. a crystal can be connected between this pin and xtal2 to form an internal oscillator circuit. an external 1 m resistor is required between the xtal1 and xtal2 pins (see figure 9). alternatively, an external clock can be connected to this pin to provide custom data rates (programming baud rate generator section). xtal2 15 o output of the crystal oscillator or buffered clock - (see also xtal1). crystal oscillator output or buffered clock output. -cd 40 i carrier detect (active low) - a logic 0 on this pin indicates that a carrier has been detected by the modem. -cts 38 i clear to send (active low) - a logic 0 on the -cts pin indicates the modem or data set is ready to accept transmit data from the 580. status can be tested by reading msr bit-4. this pin only affects the transmit and receive operations when auto cts function is enabled via the enhanced feature register (efr) bit-7, for hardware flow control operation. -dsr 39 i data set ready (active low) - a logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the uart. this pin has no effect on the uart?s transmit or receive operation. -dtr 33 o data t erminal ready (active low) - a logic 0 on this pin indicates that the 580 is powered-on and ready. this pin can be controlled via the modem control register. writing a logic 1 to mcr bit-0 will set the -dtr output to logic 0, enabling the modem. this pin will be a logic 1 after writing a logic 0 to mcr bit-0, or after a reset. this pin has no effect on the uart?s transmit or receive operation. symbol description symbol pin signal pin description 48 type
st16c580 6 rev. 1.22 -ri 41 i ring indicator (active low) - a logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. a logic 1 transition on this input pin will generate an interrupt. -rts 32 o request to send (active low) - a logic 0 on the -rts pin indicates the transmitter has data ready and waiting to send. writing a logic 1 in the modem control register (mcr bit-1) will set this pin to a logic 0 indicating data is available. after a reset this pin will be set to a logic 1. this pin only affects the transmit and receive operations when auto rts func- tion is enabled via the enhanced feature register (efr) bit-6, for hardware flow control operation. rx / irrx 7 i receive data - this pin provides the serial receive data input to the 580. two user selectable interface options are avail- able. the first option supports the standard modem interface. the second option provides an infrared decoder interface, see figures 2/3. when using the standard modem interface, the rx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. the inactive state (no data) for the infrared decoder interface is a logic 0. mcr bit-6 selects the standard modem or infrared interface. during the local loop- back mode, the rx input pin is disabled and tx data is internally connected to the uart rx input, internally, see figure 12. tx / irtx 8 o transmit data - this pin provides the serial transmit data from the 580. two user selectable interface options are available. the first user option supports a standard modem interface. the second option provides an infrared encoder interface, see figures 2/3. when using the standard modem interface, the tx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. the inactive state (no data) for the infrared encoder/ decoder interface is a logic 0. mcr bit-6 selects the standard modem or infrared interface. during the local loop-back mode, the tx input pin is disabled and tx data is internally connected to the uart rx input, see figure 12. symbol description symbol pin signal pin description 48 type
st16c580 7 rev. 1.22 general description the 580 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-paral- lel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). data integ- rity is insured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. the st16c580 represents such an integration with greatly enhanced features. the 580 is fabricated with an advanced cmos process. the 580 is an upward solution that provides 16 bytes of transmit and receive fifo memory, instead of 16 bytes provided in the 16c550, or none in the 16c450. the 580 is designed to work with high speed modems and shared network environments, that require fast data processing time. increased performance is real- ized in the 580 by the larger transmit and receive fifo?s. this allows the external processor to handle more networking tasks within a given time. in addition, the 4 selectable levels of fifo trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environ- ment. the combination of the above greatly reduces the bandwidth requirement of the external controlling cpu, increases performance, and reduces power consumption. the 580 is capable of operation to 1.5mbps with a 24 mhz crystal or external clock input. with a crystal of 7.3728 mhz and through a software option, the user can select data rates up to 460.8kbps. the rich feature set of the 580 is available through internal registers. automatic hardware/software flow control, selectable transmit and receive fifo trigger levels, selectable tx and rx baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. following a power on reset or an external reset, the 580 is software compatible with previous generation of uarts, 16c450 and 16c550. functional descriptions internal registers the 580 provides 15 internal registers for monitoring and control. these registers are shown in table 3 below. twelve registers are similar to those already available in the standard 16c550. these registers function as data holding registers (thr/rhr), interrupt status and con- trol registers (ier/isr), a fifo control register (fcr), line status and control registers, (lcr/lsr), modem status and control registers (mcr/msr), program- mable data rate (clock) control registers (dll/dlm), and a user assessable scratchpad register (spr). beyond the general 16c550 features and capabilities, the 580 offers an enhanced feature register set (efr, xon/xoff 1-2) that provides on board hardware/software flow control. register functions are more fully described in the following paragraphs.
st16c580 8 rev. 1.22 table 3, internal register decode a2 a1 a0 read mode write mode general register set (thr/rhr, ier/isr, mcr/msr, lcr/lsr, spr): 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register 0 1 0 interrupt status register fifo control register 0 1 1 line control register 1 0 0 modem control register 1 0 1 line status register 1 1 0 modem status register 1 1 1 scratchpad register scratchpad register baud rate register set (dll/dlm): note *3 0 0 0 lsb of divisor latch lsb of divisor latch 0 0 1 msb of divisor latch msb of divisor latch enhanced register set (efr, xon/off 1-2): note *4 0 1 0 enhanced feature register enhanced feature register 1 0 0 xon-1 word xon-1 word 1 0 1 xon-2 word xon-2 word 1 1 0 xoff-1 word xoff-1 word 1 1 1 xoff-2 word xoff-2 word note *3 : these registers are accessible only when lcr bit-7 is set to a logic 1. note *4 : enhanced feature register, xon 1,2 and xoff 1,2 are accessible only when the lcr is set to ?bf? (hex).
st16c580 9 rev. 1.22 fifo operation the 16 byte transmit and receive data fifo?s are enabled by the fifo control register (fcr) bit-0. with 16c550 devices, the user can set the receive trigger level but not the transmit trigger level. the 580 provides independent trigger levels for both receiver and transmitter. to remain compatible with st16c550, the transmit interrupt trigger level is set to 1 following a reset. it should be noted that the user can set the transmit trigger levels by writing to the fcr register, but activation will not take place until efr bit- 4 is set to a logic 1. the receiver fifo section includes a time-out function to ensure data is delivered to the external cpu. an interrupt is generated whenever the receive holding register (rhr) has not been read following the loading of a character or the receive trigger level has not been reached. (see hardware flow control for a description of this timing). hardware flow control when automatic hardware flow control is enabled, the 580 monitors the -cts pin for a remote buffer overflow indication and controls the -rts pin for local buffer overflows. automatic hardware flow control is se- lected by setting bits 6 (rts) and 7 (cts) of the efr register to a logic 1. if -cts transitions from a logic 0 to a logic 1 indicating a flow control request, isr bit- 5 will be set to a logic 1 (if enabled via ier bit 6-7), and the 580 will suspend tx transmissions as soon as the stop bit of the character in process is shifted out. transmission is resumed after the -cts input returns to a logic 0, indicating more data may be sent. with the auto rts function enabled, an interrupt is generated when the receive fifo reaches the pro- grammed trigger level. the -rts pin will not be forced to a logic 1 (rts off), until the receive fifo reaches the next trigger level . however, the -rts pin will return to a logic 0 after the data buffer (fifo) is unloaded to the next trigger level below the pro- grammed trigger level. however, under the above described conditions the 580 will continue to accept data until the receive fifo is full. selected int -rts -rts trigger pin logic ?1? logic ?0? level activation (characters) (characters) (characters) 1140 4481 88 14 4 14 14 14 8
st16c580 10 rev. 1.22 software flow control when software flow control is enabled, the 580 com- pares one or two sequential receive data characters with the programmed xon or xoff-1,2 character value(s). if receive character(s) (rx) match the pro- grammed values, the 580 will halt transmission (tx) as soon as the current character(s) has completed transmission. when a match occurs, the receive ready (if enabled via xoff ier bit-5) flags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. following a suspension due to a match of the xoff characters values, the 580 will monitor the receive data stream for a match to the xon-1,2 character value(s). if a match is found, the 580 will resume operation and clear the flags (isr bit- 4). reset initially sets the contents of the xon/xoff 8-bit flow control registers to a logic 0. following reset the user can write any xon/xoff value desired for software flow control. different conditions can be set to detect xon/xoff characters and suspend/resume transmis- sions. when double 8-bit xon/xoff characters are selected, the 580 compares two consecutive receive characters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx transmis- sions accordingly. under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the 580 automati- cally sends an xoff message (when enabled) via the serial tx output to the remote modem. the 580 sends the xoff-1,2 characters as soon as received data passes the programmed trigger level. to clear this condition, the 580 will transmit the programmed xon- 1,2 characters as soon as receive data drops below the programmed trigger level. special feature software flow control a special feature is provided to detect an 8-bit charac- ter when bit-5 is set in the enhanced feature register (efr). when this character is detected, it will be placed on the user accessible data stack along with normal incoming rx data. this condition is selected in conjunction with efr bits 0-3. note that software flow control should be turned off when using this special mode by setting efr bit 0-3 to a logic 0. the 580 compares each incoming receive character with xoff-2 data. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indicate detection of special character (see figure 9). although the internal register table shows each x- register with eight bits of character information, the actual number of bits is dependent on the pro- grammed word length. line control register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. bit-0 in the x-registers corresponds with the lsb bit for the receive character. time-out interrupts three special interrupts have been added to monitor the hardware and software flow control. the interrupts are enabled by ier bits 5-7. care must be taken when handling these interrupts. following a reset the trans- mitter interrupt is enabled, the 580 will issue an interrupt to indicate that transmit holding register is empty. this interrupt must be serviced prior to con- tinuing operations. the lsr register provides the current singular highest priority interrupt only. it could be noted that cts and rts interrupts have lowest interrupt priority. a condition can exist where a higher priority interrupt may mask the lower priority cts/ rts interrupt(s). only after servicing the higher pend- ing interrupt will the lower priority cts/ rts interrupt(s) be reflected in the status register. servic- ing the interrupt without investigating further interrupt conditions can result in data errors. when two interrupt conditions have the same priority, it is important to service these interrupts correctly. receive data ready and receive time out have the same interrupt priority (when enabled by ier bit-3). the receiver issues an interrupt after the number of characters have reached the programmed trigger
st16c580 11 rev. 1.22 c1 22pf c2 33pf x1 1.8432 mhz r1 50-120 r2 1m xta l 1 xta l 2 crystal oscillator connection level. in this case the 580 fifo may hold more charac- ters than the programmed trigger level. following the removal of a data byte, the user should recheck lsr bit- 0 for additional characters. a receive time out will not occur if the receive fifo is empty. the time out counter is reset at the center of each stop bit received or each time the receive holding register (rhr) is read (see figure 10, receive time-out interrupt). the actual time out value is t ( t ime out length in bits) = 4 x p ( p rogrammed word length) + 12. to convert the time out value to a character value, the user has to consider the complete word length, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1x, 1.5x, or 2x bit times. example -a: if the user programs a word length of 7, with no parity and one stop bit, the time out will be: t = 4 x 7( programmed word length) +12 = 40 bit times. the character time will be equal to 40 / 9 = 4.4 characters, or as shown in the fully worked out ex- ample: t = [(programmed word length = 7) + (stop bit = 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4 characters. example -b: if the user programs the word length = 7, with parity and one stop bit, the time out will be: t = 4 x 7(programmed word length) + 12 = 40 bit times. character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters. programmable baud rate generator the 580 supports high speed modem technologies that have increased input data rates by employing data compression schemes. for example a 33.6kbps modem that employs data compression may require a 115.2kbps input data rate. a 128.0kbps isdn modem that supports data compression may need an input data rate of 460.8kbps. the 580 can support a stan- dard data rate of 921.6kbps. single baud rate generator is provided for the trans- mitter and receiver, allowing independent tx/rx channel control. the programmable baud rate gen- erator is capable of accepting an input clock up to 24 mhz, as required for supporting a 1.5mbps data rate. the 580 can be configured for internal or external clock operation. for internal clock oscillator operation, an industry standard microprocessor crystal (parallel reso- nant/ 22-33 pf load) is connected externally between the xtal1 and xtal2 pins, with an external 1 m resistor across it. alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. the generator divides the input 16x clock by any divisor from 1 to 2 16 -1. the 580 divides the basic crystal or external clock by 16. further division of this 16x clock provides two table rates to support low and high data rate applications using the same system design. the two rate tables are selectable through the internal register, mcr bit-7. setting mcr bit-7 to a logic 1 provides an additional divide by 4 whereas, setting mcr bit-7 to a logic 0 only divides by 1. (see table 4 and figure 11). the frequency of the - baudout output pin is exactly 16x (16 times) of the selected baud rate (-baudout =16 x baud rate). customized baud rates can be achieved by selecting the proper divisor values for the msb and lsb sec- tions of baud rate generator. programming the baud rate generator registers
st16c580 12 rev. 1.22 divide by 1 logic x tal1 x tal2 divide by 4 logic clock oscillator logic baudrate generator logic -baudou t mcr bit-7=0 mcr bit-7=1 crystal oscillator or external clock 1x / 4x selection dlm (msb) and dll (lsb) provides a user capability for selecting the desired final baud rate. the example in table 4 below, shows the two selectable baud rate tables available when using a 7.3728 mhz crystal. table 4, baud rate generator programming table (7.3728 mhz clock): output output user user dlm dll baud rate baud rate 16 x clock 16 x clock program program mcr mcr divisor divisor value value bit-7=1 bit-7=0 (decimal) (hex) (hex) (hex) 50 200 2304 900 09 00 75 300 1536 600 06 00 150 600 768 300 03 00 300 1200 384 180 01 80 600 2400 192 c0 00 c0 1200 4800 96 60 00 60 2400 9600 48 30 00 30 4800 19.2k 24 18 00 18 7200 28.8k 16 10 00 10 9600 38.4k 12 0c 00 0c 19.2k 76.8k 6 06 00 06 38.4k 153.6k 3 03 00 03 57.6k 230.4k 2 02 00 02 115.2k 460.8k 1 01 00 01
st16c580 13 rev. 1.22 dma operation the 580 fifo trigger level provides additional flexibil- ity to the user for block mode operation. lsr bits 5-6 provide an indication when the transmitter is empty or has an empty location(s). the user can optionally operate the transmit and receive fifo?s in the dma mode (fcr bit-3). when the transmit and receive fifo?s are enabled and the dma mode is deactivated (dma mode ?0?), the 580 activates the interrupt output pin for each data transmit or receive operation. when dma mode is activated (dma mode ?1?), the user takes the advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the preset trigger level. in this mode, the 580 sets the interrupt output pin when characters in the transmit fifo?s are below the transmit trigger level, or the characters in the receive fifo?s are above the receive trigger level. sleep mode the 580 is designed to operate with low power con- sumption. a special sleep mode is included to further reduce power consumption when the chip is not being used. with efr bit-4 and ier bit-4 enabled (set to a logic 1), the 580 enters the sleep mode but resumes normal operation when a start bit is detected, a change of state on any of the modem input pins rx, -ri, -cts, -dsr, -cd, or transmit data is provided by the user. if the sleep mode is enabled and the 580 is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user. in any case, the sleep mode will not be entered while an interrupt(s) is pending. the 580 will stay in the sleep mode of operation until it is disabled by setting ier bit-4 to a logic 0. loop-back mode the internal loop-back capability allows onboard diag- nostics. in the loop-back mode the normal modem interface pins are disconnected and reconfigured for loop-back internally. in this mode msr bits 4-7 are also disconnected. however, mcr register bits 0-3 can be used for controlling loop-back diagnostic testing. in the loop-back mode op1 and op2 in the mcr register (bits 0-1) control the modem -ri and -cd inputs respectively. mcr signals -dtr and -rts (bits 0-1) are used to control the modem -cts and -dsr inputs respectively. the transmitter output (tx) and the receiver input (rx) are disconnected from their associated interface pins, and instead are connected together internally (see figure 12). the -cts, -dsr, -cd, and -ri are disconnected from their normal modem control inputs pins, and instead are connected internally to -dtr, -rts, -op1 and -op2. loop-back test data is entered into the transmit holding register via the user data bus interface, d0-d7. the transmit uart serializes the data and passes the serial data to the receive uart via the internal loop-back connec- tion. the receive uart converts the serial data back into parallel data that is then made available at the user data interface, d0-d7. the user optionally com- pares the received data to the initial transmitted data for verifying error free operation of the uart tx/rx circuits. in this mode , the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational. however, the interrupts can only be read using lower four bits of the modem control register (mcr bits 0-3) instead of the four modem status register bits 4-7. the interrupts are still con- trolled by the ier.
st16c580 14 rev. 1.22 d0-d7 -ior,ior -iow,iow reset a0-a2 -as cs0,cs1 -cs2 int -rxrdy -txrdy tx rx data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers flow control logic transmit shift register receive fifo registers flow control logic receive shift register inter connect bus lines & control signals clock & baud rate generator xtal1 rclk xtal2 -baudout -ddis ir encoder ir decoder -cts -rts -dtr -dsr -ri -cd -op1 -op2 mcr bit-4=1 figure 12, internal loop-back mode diagram
st16c580 15 rev. 1.22 register functional descriptions the following table delineates the assigned bit functions for the fifteen 580 internal registers. the assigned bit functions are more fully defined in the following paragraphs. table 5, st16c580 internal registers a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 [default] note *5 general register set 0 0 0 rhr [xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 thr [xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier [00] cts rts xoff sleep modem receive transmit receive interrupt interrupt interrupt mode status line holding holding interrupt status register register interrupt 0 1 0 fcr [00] rcvr rcvr tx tx dma xmit rcvr fifo trigger trigger trigger trigger mode fifo fifo enable (msb) (lsb) (msb) (lsb) select reset reset 0 1 0 isr [01] fifo?s fifo?s int int int int int int enabled enabled priority priority priority priority priority status bit-4 bit-3 bit-2 bit-1 bit-0 0 1 1 lcr [00] divisor set set even parity stop word word latch break parity parity enable bits length length enable bit-1 bit-0 1 0 0 mcr [00] clock ir 0 loop -op2 -op1 -rts -dtr select enable back 1 0 1 lsr [60] fifo trans. trans. break framing parity overrun receive data empty holding interrupt error error error data error empty ready 1 1 0 msr [x0] cd ri dsr cts delta delta delta delta -cd -ri -dsr -cts 1 1 1 spr [ff] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 special register set: note *3 0 0 0 dll [xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 dlm [xx] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8
st16c580 16 rev. 1.22 a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 [default] note *5 enhanced register set: note *4 0 1 0 efr [00] auto auto special enable cont-3 cont-2 cont-1 cont-0 cts rts char. ier tx,rx tx,rx tx,rx tx,rx select bits 4-7, control control control control isr, fcr bits 4-5, mcr bits 5-7 1 0 0 xon-1 [00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon-2 [00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 1 1 0 xoff-1 [00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff-2 [00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 note *3: the special register set is accessible only when lcr bit-7 is set to a logic 1. note *4: enhanced feature register, xon 1,2 and xoff 1,2 are accessible only when lcr is set to ?bf? hex note *5: the value represents the register?s initialized hex value. an ?x? signifies a 4-bit un-initialize nibble.
st16c580 17 rev. 1.22 transmit and receive holding register the serial transmitter section consists of an 8-bit transmit hold register (thr) and transmit shift register (tsr). the status of the thr is provided in the line status register (lsr). writing to the thr transfers the contents of the data bus (d7-d0) to the thr, providing that the thr or tsr is empty. the thr empty flag in the lsr register will be set to a logic 1 when the transmitter is empty or when data is transferred to the tsr. note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = fifo full, logic 1= at least one fifo location available). the serial receive section also contains an 8-bit receive holding register, rhr. receive data is removed from the 580 and receive fifo by reading the rhr register. the receive section provides a mechanism to prevent false starts. on the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at 16x clock rate. after 7 1/2 clocks the start bit time should be shifted to the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assem- bling a false character. receiver status codes will be posted in the lsr. interrupt enable register (ier) the interrupt enable register (ier) masks the inter- rupts from receiver ready, transmitter empty, line status and modem status registers. these interrupts would normally be seen on the 580 int output pin. ier vs receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = a logic 1) and receive interrupts (ier bit-0 = logic 1) are enabled, the receive interrupts and register status will reflect the following: a) the receive data available interrupts are issued to the external cpu when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b) fifo status will also be reflected in the user acces- sible isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. c) the data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is reset when the fifo is empty. ier vs receive/transmit fifo polled mode op- eration when fcr bit-0 equals a logic 1; resetting ier bits 0-3 enables the 580 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a) lsr bit-0 will be a logic 1 as long as there is one byte in the receive fifo. b) lsr bit 1-4 will indicate if an overrun error occurred. c) lsr bit-5 will indicate when the transmit fifo is empty. d) lsr bit-6 will indicate when both the transmit fifo and transmit shift register are empty. e) lsr bit-7 will indicate any fifo data errors. ier bit-0: logic 0 = disable the receiver ready interrupt. (normal default condition) logic 1 = enable the receiver ready interrupt. ier bit-1: logic 0 = disable the transmitter empty interrupt. (normal default condition) logic 1 = enable the transmitter empty interrupt. ier bit-2: logic 0 = disable the receiver line status interrupt. (normal default condition) logic 1 = enable the receiver line status interrupt.
st16c580 18 rev. 1.22 ier bit-3: logic 0 = disable the modem status register interrupt. (normal default condition) logic 1 = enable the modem status register interrupt. ier bit -4: logic 0 = disable sleep mode. (normal default condi- tion) logic 1 = enable sleep mode. see sleep mode section for details ier bit-5: logic 0 = disable the software flow control, receive xoff interrupt. (normal default condition) logic 1 = enable the software flow control, receive xoff interrupt. see software flow control section for details. ier bit-6: logic 0 = disable the rts interrupt. (normal default condition) logic 1 = enable the rts interrupt. the 580 issues an interrupt when the rts pin transitions from a logic 0 to a logic 1. ier bit-7: logic 0 = disable the cts interrupt. (normal default condition) logic 1 = enable the cts interrupt. the 580 issues an interrupt when cts pin transitions from a logic 0 to a logic 1. fifo control register (fcr) this register is used to enable the fifo?s, clear the fifo?s, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: dma mode mode 0 set and enable the interrupt for each single transmit or receive operation, and is similar to the st16c450 mode. transmit ready (-txrdy) will go to a logic 0 when ever an empty transmit space is available in the transmit holding register (thr). receive ready (-rxrdy) will go to a logic 0 when- ever the receive holding register (rhr) is loaded with a character. mode 1 set and enable the interrupt in a block mode operation. the transmit interrupt is set when the transmit fifo is below the programmed trigger level. -txrdy remains a logic 0 as long as one empty fifo location is available. the receive interrupt is set when the receive fifo fills to the programmed trigger level. however the fifo continues to fill regardless of the programmed level until the fifo is full. -rxrdy remains a logic 0 as long as the fifo fill level is above the programmed trigger level. fcr bit-0: logic 0 = disable the transmit and receive fifo. (normal default condition) logic 1 = enable the transmit and receive fifo. this bit must be a ?1? when other fcr bits are written to or they will not be programmed. fcr bit-1: logic 0 = no fifo receive reset. (normal default condition) logic 1 = clears the contents of the receive fifo and resets the fifo counter logic (the receive shift regis- ter is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. fcr bit-2: logic 0 = no fifo transmit reset. (normal default condition) logic 1 = clears the contents of the transmit fifo and resets the fifo counter logic (the transmit shift regis- ter is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. fcr bit-3: logic 0 = set dma mode ?0?. (normal default condi- tion) logic 1 = set dma mode ?1.? transmit operation in mode ?0?: when the 580 is in the st16c450 mode (fifo?s disabled, fcr bit-0 = logic 0) or in the fifo mode (fifo?s enabled, fcr bit-0 = logic 1, fcr bit-3 = logic 0) and when there are no characters in the transmit fifo or transmit holding register, the -txrdy pin will be a
st16c580 19 rev. 1.22 logic 0. once active the -txrdy pin will go to a logic 1 after the first character is loaded into the transmit holding register. receive operation in mode ?0?: when the 580 is in mode ?0? (fcr bit-0 = logic 0) or in the fifo mode (fcr bit-0 = logic 1, fcr bit-3 = logic 0) and there is at least one character in the receive fifo, the -rxrdy pin will be a logic 0. once active the -rxrdy pin will go to a logic 1 when there are no more characters in the receiver. transmit operation in mode ?1?: when the 580 is in fifo mode ( fcr bit-0 = logic 1, fcr bit-3 = logic 1 ), the -txrdy pin will be a logic 1 when the transmit fifo is completely full. it will be a logic 0 if one or more fifo locations are empty. receive operation in mode ?1?: when the 580 is in fifo mode (fcr bit-0 = logic 1, fcr bit-3 = logic 1) and the trigger level has been reached, or a receive time out has occurred, the - rxrdy pin will go to a logic 0. once activated, it will go to a logic 1 after there are no more characters in the fifo. fcr bit 4-5: (logic 0 or cleared is the default condi- tion, tx trigger level = 1) these bits are used to set the trigger level for the transmit fifo interrupt. the st16c580 will issue a transmit empty interrupt when the number of charac- ters in fifo drops below the selected trigger level. bit-5 bit-4 tx fifo trigger level 00 1 01 4 10 8 11 14 fcr bit 6-7: (logic 0 or cleared is the default condi- tion, rx trigger level =8) these bits are used to set the trigger level for the receive fifo interrupt. an interrupt is generated when the number of characters in the fifo equals the programmed trigger level. how- ever the fifo will continue to be loaded until it is full. bit-7 bit-6 rx fifo trigger level 00 1 01 4 10 8 11 14 interrupt status register (isr) the 580 provides six levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six inter- rupt status bits. performing a read cycle on the isr will provide the user with the highest pending interrupt level to be serviced. no other interrupts are acknowl- edged until the pending interrupt is serviced. when- ever the interrupt status register is read, the interrupt status is cleared. however it should be noted that only the current pending interrupt is cleared by the read. a lower level interrupt may be seen after rereading the interrupt status bits. the interrupt source table 6 (below) shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels:
st16c580 20 rev. 1.22 table 6, interrupt source table priority [ isr bits ] level bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 source of the interrupt 1 000110 lsr (receiver line status register) 2 000100 rxrdy (received data ready) 2 001100 rxrdy (receive data time out) 3 000010 txrdy ( transmitter holding register empty) 4 000000 msr (modem status register) 5 010000 rxrdy (received xoff signal)/ special character 6 100000 cts, rts change of state isr bit-0: logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. logic 1 = no interrupt pending. (normal default condi- tion) isr bit 1-3: (logic 0 or cleared is the default condition) these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see interrupt source table). isr bit 4-5: (logic 0 or cleared is the default condition) these bits are enabled when efr bit-4 is set to a logic 1. isr bit-4 indicates that matching xoff character(s) have been detected. isr bit-5 indicates that cts, rts have been generated. note that once set to a logic 1, the isr bit-4 will stay a logic 1 until xon character(s) are received. isr bit 6-7: (logic 0 or cleared is the default condition) these bits are set to a logic 0 when the fifo is not being used. they are set to a logic 1 when the fifo?s are enabled line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr bit 0-1: (logic 0 or cleared is the default condition) these two bits specify the word length to be transmitted or received. bit-1 bit-0 word length 00 5 01 6 10 7 11 8 lcr bit-2: (logic 0 or cleared is the default condition) the length of stop bit is specified by this bit in conjunction with the programmed word length. bit-2 word length stop bit length (bit time(s)) 0 5,6,7,8 1 1 5 1-1/2 1 6,7,8 2 lcr bit-3: parity or no parity can be selected via this bit. logic 0 = no parity (normal default condition) logic 1 = a parity bit is generated during the transmis- sion, receiver checks the data and parity for transmis- sion errors.
st16c580 21 rev. 1.22 lcr bit-4: if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted data. the receiver must be programmed to check the same format. (normal default condition) logic 1 = even parity is generated by forcing an even the number of logic 1?s in the transmitted. the receiver must be programmed to check the same format. lcr bit-5: if the parity bit is enabled, lcr bit-5 selects the forced parity format. lcr bit-5 = logic 0, parity is not forced (normal default condition) lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr lcr lcr parity selection bit-5 bit-4 bit-3 x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity ?1? 1 1 1 forced parity ?0? lcr bit-6: when enabled the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr bit-6 to a logic 0. logic 0 = no tx break condition. (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 for alerting the remote receiver to a line break condition. lcr bit-7: the internal baud rate counter latch and enhance feature mode enable. logic 0 = divisor latch disabled. (normal default condition) logic 1 = divisor latch and enhanced feature register enabled. modem control register (mcr) this register controls the interface with the modem or a peripheral device. mcr bit-0: logic 0 = force -dtr output to a logic 1. (normal default condition) logic 1 = force -dtr output to a logic 0. mcr bit-1: logic 0 = force -rts output to a logic 1. (normal default condition) logic 1 = force -rts output to a logic 0. automatic rts may be used for hardware flow control by enabling efr bit-6 (see efr bit-6). mcr bit-2: logic 0 = set -op1 output to a logic 1. (normal default condition) logic 1 = set -op1 output to a logic 0. mcr bit-3: logic 0 = set -op2 output to a logic 1. (normal default condition) logic 1 = set -op2 output to a logic 0. mcr bit-4: logic 0 = disable loop-back mode. (normal default condition) logic 1 = enable local loop-back mode (diagnostics). mcr bit-5: not used. mcr bit-6: logic 0 = enable modem receive and transmit input/ output interface. (normal default condition) logic 1 = enable infrared irda receive and transmit
st16c580 22 rev. 1.22 inputs/outputs. while in this mode, the tx/rx output/ inputs are routed to the infrared encoder/decoder. the data input and output levels will conform to the irda infrared interface requirement. as such, while in this mode the infrared tx output will be a logic 0 during idle data conditions. mcr bit-7: logic 0 = divide by one. the input clock (crystal or external) is divided by sixteen and then presented to the programmable baud rate generator (bgr) with- out further modification, i.e., divide by one. (normal, default condition) logic 1 = divide by four. the divide by one clock described in mcr bit-7 equals a logic 0, is further divided by four (also see programmable baud rate generator section). line status register (lsr) this register provides the status of data transfers between. the 580 and the cpu. lsr bit-0: logic 0 = no data in receive holding register or fifo. (normal default condition) logic 1 = data has been received and is saved in the receive holding register or fifo. lsr bit-1: logic 0 = no overrun error. (normal default condition) logic 1 = overrun error. a data overrun error occurred in the receive shift register. this happens when addi- tional data arrives while the fifo is full. in this case the previous data in the shift register is overwritten. note that under this condition the data byte in the receive shift register is not transfer into the fifo, therefore the data in the fifo is not corrupted by the error. lsr bit-2: logic 0 = no parity error (normal default condition) logic 1 = parity error. the receive character does not have correct parity information and is suspect. in the fifo mode, this error is associated with the character at the top of the fifo. lsr bit-3: logic 0 = no framing error (normal default condition). logic 1 = framing error. the receive character did not have a valid stop bit(s). in the fifo mode this error is associated with the character at the top of the fifo. lsr bit-4: logic 0 = no break condition (normal default condi- tion) logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. lsr bit-5: this bit is the transmit holding register empty indi- cator. this bit indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to cpu when the thr interrupt enable is set. the thr bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. the bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the cpu. in the fifo mode this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. lsr bit-6: this bit is the transmit empty indicator. this bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmit fifo and transmit shift register are both empty. lsr bit-7: logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current fifo data. this bit is cleared when lsr register is read. modem status register (msr) this register provides the current state of the control interface signals from the modem, or other peripheral
st16c580 23 rev. 1.22 device that the 580 is connected to. four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a control input from the modem changes state. these bits are set to a logic 0 whenever the cpu reads this register. msr bit-0: logic 0 = no -cts change (normal default condition) logic 1 = the -cts input to the 580 has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-1: logic 0 = no -dsr change (normal default condition) logic 1 = the -dsr input to the 580 has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-2: logic 0 = no -ri change (normal default condition) logic 1 = the -ri input to the 580 has changed from a logic 0 to a logic 1. a modem status interrupt will be generated. msr bit-3: logic 0 = no -cd change (normal default condition) logic 1 = indicates that the -cd input to the has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-4: -cts functions as hardware flow control signal input if it is enabled via efr bit-7. the transmit holding register flow control is enabled/disabled by msr bit-4. flow control (when enabled) allows the starting and stopping the transmissions based on the external modem -cts signal. a logic 1 at the -cts pin will stop 580 transmissions as soon as current character has finished transmission. normally msr bit-4 bit is the compliment of the -cts input. however in the loop-back mode, this bit is equivalent to the rts bit in the mcr register. msr bit-5: dsr (active high, logical 1). normally this bit is the compliment of the -dsr input. in the loop-back mode, this bit is equivalent to the dtr bit in the mcr register. msr bit-6: ri (active high, logical 1). normally this bit is the compliment of the -ri input. in the loop-back mode this bit is equivalent to the op1 bit in the mcr register. msr bit-7: cd (active high, logical 1). normally this bit is the compliment of the -cd input. in the loop-back mode this bit is equivalent to the op2 bit in the mcr register. scratchpad register (spr) the st16c580 provides a temporary data register to store 8 bits of user information. enhanced feature register (efr) enhanced features are enabled or disabled using this register. bits-0 through 4 provide single or dual character software flow control selection. when the xon1 and xon2 and/or xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated into two sequen- tial characters. efr bit 0-3: (logic 0 or cleared is the default condi- tion) combinations of software flow control can be selected by programming these bits.
st16c580 24 rev. 1.22 table 7, software flow control functions cont-3 cont-2 cont-1 cont-0 tx, rx software flow controls 0 0 x x no transmit flow control 1 0 x x transmit xon1/xoff1 0 1 x x transmit xon2/xoff2 1 1 x x transmit xon1 and xon2/xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1/xoff1 x x 0 1 receiver compares xon2/xoff2 1011 transmit xon1/ xoff1. receiver compares xon1 and xon2, xoff1 and xoff2 0111 transmit xon2/xoff2 receiver compares xon1 and xon2/xoff1 and xoff2 1111 transmit xon1 and xon2/xoff1 and xoff2 receiver compares xon1 and xon2/xoff1 and xoff2 0011no transmit flow control receiver compares xon1 and xon2/xoff1 and xoff2 efr bit-4: enhanced function control bit. the content of the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 can be modified and latched. after modifying any bits in the enhanced registers, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents existing software from altering or overwriting the 580 enhanced functions. logic 0 = disable/latch enhanced features. ier bits 4- 7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are saved to retain the user settings, then ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are initialized to the default values shown in the internal resister table. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are set to a logic 0 to be compatible with st16c550 mode. (normal default condition). logic 1 = enables the enhanced functions. when this bit is set to a logic 1 all enhanced features of the 580 are enabled and user settings stored during a reset will be restored. efr bit-5: logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. the 580 compares each incoming receive character with xoff- 2 data. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indicate detection of special character. bit-0 in the x-registers corresponds with the lsb bit for the receive character. when this feature is enabled, the normal software flow control must be disabled (efr bits 0-3 must be set to a logic 0). efr bit-6: automatic rts may be used for hardware flow control by enabling efr bit-6. when auto rts is selected, an interrupt will be generated when the receive fifo is filled to the programmed trigger level and -rts will go to a logic 1 at the next trigger level. -rts will return to a logic 0 when data is unloaded below the next lower trigger level (programmed trigger level -1). the state of this register bit changes with the status of the
st16c580 25 rev. 1.22 hardware flow control. -rts functions normally when hardware flow control is disabled. 0 = automatic rts flow control is disabled. (normal default condition) 1 = enable automatic rts flow control. efr bit-7: automatic cts flow control. logic 0 = automatic cts flow control is disabled. (normal default condition) logic 1 = enable automatic cts flow control. trans- mission will stop when -cts goes to a logical 1. transmission will resume when the -cts pin returns to a logical 0. st16c580 external reset conditions registers reset state ier ier bits 0-7 = logic 0 isr isr bit-0=1, isr bits 1-7 = logic 0 lcr, mcr bits 0-7 = logic 0 lsr lsr bits 0-4 = logic 0, lsr bits 5-6 = logic 1 lsr, bit 7 = logic 0 msr msr bits 0-3 = logic 0, msr bits 4-7 = logic levels of the input signals fcr, efr bits 0-7 = logic 0 signals reset state tx logic 1 -op1 logic 1 -op2 logic 1 -rts logic 1 -dtr logic 1 -rxrdy logic 1 -txrdy logic 0 int logic 0
st16c580 26 rev. 1.22 ac electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. t 1w ,t 2w clock pulse duration 17 17 ns t 3w oscillator/clock frequency 8 24 mhz t 4w address strobe width 35 25 ns t 5s address setup time 5 0 ns t 5h address hold time 5 5 ns t 6s address setup time 5 0 ns t 6h chip select hold time 0 0 ns t 7d -ior delay from chip select 10 10 ns note 1: t 7w -ior strobe width 35 25 ns t 7h chip select hold time from -ior 0 0 ns note 1: t 8d -ior delay from address 10 10 ns note 1: t 9d read cycle delay 40 30 ns t 11d -ior to -ddis delay 15 10 ns 100 pf load t 12d delay from -ior to data 35 25 ns t 12h data disable time 25 15 ns t 13d -iow delay from chip select 10 10 ns note 1: t 13w -iow strobe width 40 25 ns t 13h chip select hold time from -iow 0 0 ns t 14d -iow delay from address 10 10 ns note 1: t 15d write cycle delay 40 30 ns t 16s data setup time 20 15 ns t 16h data hold time 5 5 ns t 17d delay from -iow to output 50 40 ns 100 pf load t 18d delay to set interrupt from modem 40 35 ns 100 pf load input t 19d delay to reset interrupt from -ior 40 35 ns 100 pf load t 20d delay from stop to set interrupt 1 1 rclk t 21d delay from -ior to reset interrupt 45 40 ns 100 pf load t 22d delay from stop to interrupt 45 40 ns t 23d delay from initial int reset to transmit 8 2 4 8 24 rclk start t 24d delay from -iow to reset interrupt 45 40 ns t 25d delay from stop to set -rxrdy 1 1 rclk t 26d delay from -ior to reset -rxrdy 45 40 ns t 27d delay from -iow to set -txrdy 45 40 ns t 28d delay from start to reset -txrdy 8 8 rclk t r reset pulse width 40 40 ns n baud rate devisor 1 2 16 -1 1 2 16 -1 rclk note 1: applicable only when -as is tied low. symbol parameter limits limits units conditions 3.3 5.0 min max min max
st16c580 27 rev. 1.22 absolute maximum ratings supply range 7 volts voltage at any pin gnd - 0.3 v to vcc +0.3 v operating temperature -40 c to +85 c storage temperature -65 c to 150 c package dissipation 500 mw dc electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low level -0.3 0.8 -0.5 0.8 v v ih input high level 2.0 2.2 vcc v v ol output low level on all outputs 0.4 v i ol = 5 ma v ol output low level on all outputs 0.4 v i ol = 4 ma v oh output high level 2.4 v i oh = -5 ma v oh output high level 2.0 v i oh = -1 ma i il input leakage 10 10 a i cl clock leakage 10 10 a i cc avg power supply current 1.3 3 ma c p input capacitance 5 5 pf symbol parameter limits limits units conditions 3.3 5.0 min max min max
st16c580 28 rev. 1.22 clock timing t3w -baudout 1/2 -baudout 1/3 -baudout 1/3> -baudout t1w t2w external clock x450-ck-1
st16c580 29 rev. 1.22 general read timing -ddis d0-d7 t12d t12h x550-rd-1 -as a 0-a2 -cs2 cs1-cs0 -ior ior t4w t5s t5h t6s t6h t7w t7d t7h t9d t11d t11d t8d valid address valid active data active
st16c580 30 rev. 1.22 general write timing -as a 0-a2 -cs2 cs1-cs0 -iow iow d0-d7 t4w t5s t5h t6s t6h t13w t13d t13h t15d t16s x550-wd-1 t14d t16h valid address valid active data
st16c580 31 rev. 1.22 modem input/output timing -iow iow -rts -dtr -cd -cts -dsr int -ior ior -ri t17d t18d t18d t19d t18d x450-md-1 active active change of state change of state active active active change of state change of state change of state active active
st16c580 32 rev. 1.22 receive timing stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit rx next data start bit int -ior ior t20d t21d 16 baud rate clock x450-rx-1 active
st16c580 33 rev. 1.22 receive ready timing in none fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit rx next data start bit -rxrdy -ior ior t25d t26d x550-rx-2 active data ready active
st16c580 34 rev. 1.22 receive ready timing in fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit rx first byte that reaches the trigger level -rxrdy -ior ior t25d t26d x550-rx-3 active data ready active
st16c580 35 rev. 1.22 transmit timing stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx next data start bit int t22d t24d 16 baud rate clock x450-tx-1 -iow iow t23d active active tx ready active
st16c580 36 rev. 1.22 transmit ready timing in none fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit tx next data start bit -txrdy t28d x550-tx-2 -iow iow t27d byte #1 active active transmitter ready transmitter not ready
st16c580 37 rev. 1.22 transmit ready timing in fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx -iow iow d0-d7 -txrdy byte #16 t28d t27d x550-tx-3 fifo full active
st16c580 38 rev. 1.22 symbol min max min max inches millimeters a b a 2 a 1 1.20 0.27 1.05 0.15 1.00 0.17 0.95 0.05 0.047 0.011 0.041 0.006 0.039 0.007 0.037 0.002 note: the control dimension is the millimeter column d c 7.10 9.20 0.20 6.90 8.80 0.09 0.280 0.362 0.008 0.272 0.346 0.004 d 1 l e 7 0.75 0 0.45 0.50bsc 7 0.030 0 0.018 0.20 bsc 36 25 24 13 1 1 2 37 48 d d 1 d d 1 b e a 2 a 1 a seating plane l c 48 lead thin quad flat pack (tqfp) package outline drawing
st16c580 39 rev. 1.22 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2005 exar corporation datasheet august 2005 send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com reproduction, in part or whole, without prior written consent of exar corporation is prohibited. explanation of data sheet revisions: from to changes date 1.10 1.20 added patent number. added revision history. sept 2003 added device status to front page. 1.20 1.21 corrected -as pin description. may 2005 1.21 1.22 removed discontinued packages (40-pin pdip and 44-pin plcc) from august 2005 ordering information.

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